1. Field of the Invention
The present invention relates to semiconductor devices including trenches formed through a PN junction and, more particularly, to a MOSFET, an IGBT and the like having trench MOS gates.
2. Description of the Background Art
FIG. 25 is a cross-sectional view of a conventional IGBT of trench MOS structure. As shown in FIG. 25, an N epitaxial layer 2 is formed on a P.sup.+ substrate 1, and an N.sup.- epitaxial layer 3 is formed on the N epitaxial layer 2. On the N.sup.- epitaxial layer 3, a plurality of P well regions 4 are formed which are insulated from each other by trench isolating layers 10 each including gate polysilicon 7 and an oxide film 6 therearound. An N.sup.+ emitter region 5 is formed in the surface of each P well region 4. An emitter electrode 8 is formed over the P well regions 4, the N.sup.+ emitter regions 5 and the trench isolating layers 10. A collector electrode 9 is formed on the lower surface of the P.sup.+ substrate 1.
In the IGBT having such arrangement, when a driving voltage of not less than a threshold voltage is applied to the gate polysilicon 7, with the emitter electrode 8 grounded and a predetermined positive voltage applied to the collector electrode 9 as shown in FIG. 26, channels are formed in the P well regions 4 along the side walls of the gate polysilicon 7. Current flows through the channels, so that the IGBT turns on.
When the driving voltage applied to the gate polysilicon 7 is not more than the threshold voltage, the channels disappear, so that the IGBT turns off. In the off state, a collector voltage is maintained by a depletion layer extending toward the N.sup.- epitaxial layer 3 from a PN junction J biased in the reverse direction at the interface of the P well regions 4 and the N.sup.- epitaxial layer 3.
The conventional IGBT of trench MOS structure has the above-mentioned arrangement. An outermost P well region 4A insulatedly formed on the outside of the outermost of the plurality of trench isolating layers 10 for insulating the P well regions 4 is as deep as the other P well regions 4.
This causes the greatest electric field concentration in a bottom edge adjacent region R1 of the outermost trench isolating layer 10 which lies in the depletion layer extending from the PN junction J maintaining the collector voltage, as shown in FIG. 26, when the IGBT is off.
FIG. 27 shows a potential distribution (F1) about the bottom edge of the outermost trench isolating layer and a potential distribution (F2) about the bottom edge of another trench isolating layer when the IGBT is off. FIG. 28 shows an electric field distribution (F3) about the bottom edge of the outermost trench isolating layer and an electric field distribution (F4) about the bottom edge of another trench isolating layer when the IGBT is off. It is apparent from FIGS. 27 and 28 that the electric field concentration generated about the bottom edge of the outermost trench isolating layer is much greater than that generated about the bottom edge of the other trench isolating layers.
The semiconductor device including the trench structure that separates the PN junction such as an IGBT of trench MOS structure presents a problem in that, since the electric field concentration about the bottom edge of the outermost trench structure is much greater than that of the other regions when the PN junction is biased in the reverse direction, a device breakdown voltage is lowered which is the breakdown voltage at the PN junction of the semiconductor device.